16 December 2006

Back in the early days of blogs, it was suggested that one of the uses for them might be real-time coverage of conferences and such, by journalists and others posting their notes "live," or at least soon after the event.

I've thought of doing that, and I always feel like I'm abandoning my readers when I go off to a conference and don't post much for days. The problem is that my notes tend to be very abbreviated. Not only don't they necessarily reflect well on either my subject or me, but they don't necessarily make any sense out of context. I always feel like I should make the entry more article-like, which of course is more work.

For example, the following is from the Applied Materials panel discussion held last Tuesday night:
Venu Menon -- Texas Instruments -- VP Silicon Technology development

  • 32 nm is 5th node of sub-wavelength lithography
    • Litho cost a big concern

    • $50 million steppers

    • Big dice, multiple Vts.

  • More strain

  • No convergence on high-k or metal
    • integration issues

    • need to be very reliable, very low cost

  • No Lgate, Vdd scaling
    • Need lots of design assists with power management

  • Interconnects evolutionary

  • Embedded SRAM--cell stability and read current at odds with power scaling
    • 30-40% of TI parts are SRAM

    • can't live with local transistor variability

  • Fulcrum of innovation moving to design, process no longer center stage
    • we'll see fewer "allowed" designs, to allow process to optimize for narrower set of possible features

Posted 06:06 PM

13 December 2006

I'm at the IEEE Electron Device Meeting in San Francisco this week, and I've figured out how to kill any conversation.

Ask about high-k dielectrics and metal gate materials, especially for the 32 nm technology node. Very few people are willing to speculate about what the industry as a whole will do, much less go on the record regarding their own company's plans.

It's pretty clear that the long pole in the tent is the PMOS transistor. It's very difficult to find a p-type metal with a band-edge work function that will also tolerate the rest of the process. NMOS seems to be a much easier problem.

On the other hand, PMOS transistors get more benefit from strain engineering techniques, and SiGe-channel PMOS transistors have been more successful than their PMOS counterparts. So there's some talk about hybrid schemes, using different levers to match the performance of PMOS and NMOS transistors.

At least those are the possibilities that are being considered. As for the conclusions being drawn, no one is willing to say.

Posted 09:44 PM


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