10 March 2006

New activation anneals help dopants stay put

Previously published in Semiconductor Manufacturing Magazine, August 2005

Though everyone talks about silicon as the basis of the integrated circuit industry, it's important to remember that pure undoped silicon is a poor conductor. Transistors actually derive their properties from dopant atoms like boron, arsenic, and phosphorous. Dopants create high concentrations of free carriers; the junctions that control current flow lie at the boundaries between doped regions. Transistor fabrication can be viewed as an exercise in precise control of dopant concentration and placement. The source, drain, and extension locations define the channel length. The carrier density defines the drive current and other important parameters. Several different parasitic resistors and capacitors depend on sheet resistance, junction dimensions, or both. Sharp edges between doped regions give more ideal transistor behavior, while blurred doping profiles contribute to junction leakage. The success or failure of the transistor fabrication process depends on the fab's ability to place dopants in desired locations, and keep them there through subsequent steps.

Like many aspects of semiconductor manufacturing, junction formation balances competing requirements. Transistor scaling requires shorter channels and shallower junctions. According to the 2004 ITRS update, the 65 nm node sets the drain extension junction depth at 13.8 nm, and the contact junction depth at 27.5 nm. Sheet resistance, meanwhile, depends on the concentration of free carriers. For the 65 nm node, dopant concentrations in the source, drain, and extensions are likely to exceed 1019 atoms/cm3. Furthermore, dopants can only contribute carriers when they are activated, or placed at silicon sites in the crystal lattice. In conventional CMOS manufacturing, an ion beam implants dopants into the wafer, where a high temperature anneal activates them while correcting the lattice damage caused by the implant. Achieving high dopant concentrations in shallow junction regions requires high beam current, low beam energy, and activation temperatures in excess of 1000°C.

Placing ions

Beam current is, roughly speaking, the density of ions delivered by the implant system. Beam current defines the rate at which ions impact the surface, and therefore the time needed to deliver the desired dopant concentration. Beam energy is the magnitude of the field used to accelerate implanted ions. It defines the amount of momentum the ions carry. A high energy beam hits the substrate harder, does more damage, and penetrates more deeply. A low energy, high current beam delivers the desired dose more quickly, at shallower depths.

Unfortunately, the nature of ion implantation makes high beam current with low energy particularly difficult to achieve. An ion beam consists of both charged ions and free electrons, contained and directed to their destination by magnets and/or electric fields. Within the beam, ions tend to repel each other. In a high energy beam, the overall acceleration overcomes this tendency: the repulsive force between ions is less than the forward motion of the beam as a whole. In a low energy beam, on the other hand, the repulsive force is comparable to the total momentum. The beam tends to spread out, with ions moving laterally away from each other as well as forward toward the substrate. Beam current and throughput suffer.

One possible solution maintains a high energy beam through most of the ion path, then decelerates it just before impact with the wafer. Though this approach can improve beam current, it increases the risk of energy contamination. Leonard Rubin, principal scientist at Axcelis, explained that energy contamination occurs when ions and electrons in the beam recombine to create neutral particles. Neutral particles are not affected by electrical or magnetic fields, including the deceleration field. They still carry their full original energy on impact with the wafer. These particles penetrate more deeply into the wafer than decelerated ions, blurring the dopant profile and causing end-of-range defects.

Bending the beam through a magnetic field can reduce or eliminate energy contamination. The charged particles follow a curved trajectory, while neutral particles, unaffected by the field, go straight through and are caught by an appropriate trap. Beam bending tends to degrade angular precision, however. Source and drain implants require vertical implants; angular inaccuracies as small as 0.25° can cause shadowing by the gate. For non-vertical implants, poor angular control can degrade implant placement. For similar reasons, Rubin said, systems which mechanically scan the wafer across the beam may give better angular control than systems which combine mechanical scanning with electrostatic beam control.

An alternative route to high beam current at low energy replaces ions with molecules. For example, each B18H22 molecule creates 18 boron ions. Each of these will strike the wafer with about one-twentieth of the total beam energy, Rubin said. At the same time, the current carried by a B18H22 beam will be about eighteen times that of an equivalent boron beam. Molecular implants change the balance between energy and beam current, giving high throughput while implanting shallow junctions.

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Activating ions: faster is better

Implant vendors expect they will be able to meet the twin challenges of high current and low energy. The need for dopant activation poses additional problems, however. As noted above, the activation anneal places dopant atoms on lattice sites. As dopant concentrations approach the solid solubility limit, the number of available lattice sites per dopant ion shrinks. More energy is needed to create silicon lattice vacancies and fill them with dopants, and so more thermal energy is needed to ensure complete activation.

At the same time, any high temperature anneal encourages diffusion. Diffusion is driven by concentration gradients: the edges of highly doped regions tend to blur as dopants diffuse to adjacent areas of lower concentration. Boron, the smallest of the commonly used dopant ions, diffuses especially quickly. Moreover, the damage caused by the implant itself leads to transient enhanced diffusion (TED) of boron: boron diffuses more quickly than normal until the normal lattice structure is restored. Among other undesirable effects, TED can cause clustering of boron interstitials. If the local boron concentration exceeds the solid solubility limit - about 1 at. % -- the clusters can precipitate out of solution.

The diffusion rate increases with temperature. Unlike activation, which occurs quickly once an adequate energy is reached, diffusion involves physical movement of atoms over relatively long distances. The amount of diffusion thus depends on the total thermal budget of the wafer, the product of temperature and time, rather than the maximum temperature alone. If a junction is to withstand very high activation temperatures without diffusion, it can only be exposed to those temperatures for very short times.

This tradeoff between activation and diffusion is not new. Earlier attempts to balance the two led to the replacement of furnace annealing with rapid thermal annealing (RTA). RTA depends on radiant heating by halogen lamps. The thermal masses of the lamps, the wafer, and the process chamber constrain heating and cooling rates in RTA systems. According to Paul Timans, director of RTP technology at Mattson, thermal spikes from the best RTA systems last about one second.

Yet even a second is now too long. Manufacturers would like to eliminate dopant diffusion entirely. One approach to the problem seeks to extend RTA by reducing the length of time at high temperatures to milliseconds or less. In flash annealing, an arc lamp illuminates the wafer with a pulse of high intensity broadband light lasting only a few milliseconds.

Achieving a uniform temperature with a millisecond light pulse is challenging because the wafer does not present a uniform surface. Isolation trenches, gate stacks, and other circuit features have physical texture and unique chemical compositions. Thus, as Mattson Fellow Jeff Gelpey explained, optical coupling between the illumination source and the wafer varies with the circuit pattern. Broadband illumination floods the wafer with many different wavelengths. Though the response to any single wavelength is pattern dependent, spectral averaging minimizes variation in the heating characteristics. Mattson's flash annealing process first heats the wafer to an intermediate temperature using conventional RTA halogen lamps. Then, a brief pulse from the arc lamp raises the wafer to the activation temperature. This approach reduces the maximum thermal gradient, and thus the amount of thermal stress. Some diffusion may occur at the intermediate temperature, though. In research presented at the Materials Research Society's 2004 Spring Meeting, A. Satta and coworkers at IMEC and Vortek Industries (since acquired by Mattson) showed that the intermediate annealing temperature establishes the minimum junction depth.

Up until now, circuit and process designs have assumed a certain amount of diffusion, and in fact have relied on lateral diffusion to define some circuit features. If diffusion is eliminated, the implant system must be able to place ions underneath the source and drain spacers and in similar difficult locations. In some cases, use of an intermediate anneal temperature to drive carefully controlled diffusion may allow more relaxed implant specifications.

Arc lamps can achieve very short pulse times in part because the wafer bulk acts as a heat sink, Gelpey said. The top few nanometers reach the desired activation temperature quickly, while the bulk remains relatively cool. After the lamp turns off, heat from the wafer surface dissipates into the bulk. Another alternative, laser annealing, achieves even more dramatic gradients. This technique scans a laser across the surface, heating only those areas exposed to the beam at any given instant. While flash annealing achieves activation times on the order of milliseconds, laser annealing can achieve near instantaneous pulses of 10-9 seconds.

As noted above, different parts of the circuit pattern will absorb the single laser wavelength differently. Optical coupling thus determines anneal temperature, but variations in the anneal temperature can cause substantial changes in electrical characteristics. One solution to the problem, described in June 2005's issue of IEEE Transactions on Electron Devices by Akio Shima and coworkers at Hitachi, uses a polysilicon phase switch layer to control the optical coupling. This layer switches from low to high reflectance above the desired process temperature, essentially "turning off" the laser once the desired temperature is reached. Underneath, a tungsten-based absorber layer increases absorption of the laser in junction regions. Together, these layers allow precise control of the surface temperature, making it possible to melt the amorphous junction regions without damaging the surrounding crystalline silicon.

Both flash annealing and laser annealing are inherently nonequilibrium processes, Satta explained. Their very rapid heating and cooling freezes the wafer in a state which may or may not be thermodynamically stable. For example, very fast anneals can create artificially high dopant activation levels. A dopant atom might be in a thermodynamically unfavorably location, but constrained by kinetics. Subsequent thermal processes can relax these states back to equilibrium, potentially deactivating some dopants and increasing sheet resistance. Even worse, these effects can vary due to nonuniform heating, resulting in unstable junction behavior.

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Activating ions: no, cooler is better

Advanced transistor designs rely on new materials, particularly high-k dielectrics and metal gate electrodes. Though these materials are still in development, it appears likely that they will sharply reduce thermal budgets. Amorphous hafnium oxide is prone to crystallization at high temperatures, while high temperatures also increase the potential for chemical reactions within the gate stack. In work presented at the Spring 2004 MRS meeting, William Taylor and coworkers at Motorola (now Freescale Semiconductor) explained that these materials may sharply limit the maximum anneal temperature, forcing manufacturers to find another way to improve activation.

One possible low thermal budget process is solid phase epitaxial regrowth (SPE), seeks to exploit the damage inflicted by the implant to improve activation and process control. SPE first fully amorphizes the desired junction region, either with a pre-amorphizing implant like Ge, or by using a heavy ion like BF2 to create the junction region. Then, a relatively low temperature anneal (between 500° and 750°C) regrows the crystal structure, using the underlying wafer as a template. Because dopant ions are incorporated into a growing crystal lattice, rather than displacing silicon from existing lattice sites, SPE achieves activation levels approaching the solid solubility limit. Activation occurs only in the amorphous region, as the process temperature is not high enough to achieve activation in crystalline silicon.

SPE is a complex process, involving interactions among several different ion implantation steps. The optimum SPE process has not yet been identified, nor are the effects of process parameter variation understood. For example, SPE relies on the boundary between the amorphous implanted layer and the crystalline bulk to prevent transient enhanced diffusion. However, energy contamination during the implant can place some defects beyond the amorphous silicon region. These end-of-range defects will not be annealed out during regrowth, and in fact can become sinks for boron. Gettering of boron by defects at the junction edge can blur the dopant profile, or can reduce overall boron activation.

Both high and low temperature activation processes can affect the wafer's stress profile, either adding new stresses or allowing existing stress to relax. While thermal gradients have always caused stress, Taylor explained, these effects raise new concerns as manufacturers turn to strain engineering to increase carrier mobility. So far, only a few researchers have considered the interaction between engineered strain and process-induced strain. At the Spring 2005 MRS meeting, M.S. Phen and coworkers at the University of Florida discussed a study of SPE in strained silicon films. They found that the regrowth process breaks down for strain levels above 1.4%, but lower strain levels can survive SPE without loss of strain or introduction of new strain-related defects.

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Beyond ion implant

The limitations of ion implantation and rapid thermal annealing have sparked interest in a variety of alternative doping methods. Though the industry expects these techniques will be sufficient for the short term, the very strict thermal budget requirements of advanced transistor designs may require other alternatives. One possibility, plasma doping, immerses the wafer in a plasma containing the desired dopant. Plasma doping eliminates all concerns related to energy contamination or incident angle. However, it is only appropriate for very shallow dopant wells, as the energy of the plasma limits the dopant depth. Plasma doping is also extremely difficult to control. Ultrashallow junctions require high dopant concentrations, uniformly maintained across the wafer surface. The required uniformity is difficult to achieve through the random bombardment of a plasma.

Another approach, gas cluster ion beam (GCIB) technology, delivers highly energetic clusters of thousands of weakly bound atoms. Typically, the energy of each atom is less than 10 eV, far less than even low energy molecular ion implantation can achieve. Epion chief technology officer John Hautala explained that these clusters break apart when they strike the surface, dissipating their energy into a shallow (20 nm or less) surface region. Epion claims it has achieved surface boron doping levels in excess of 1022 atoms/cm3.

Looking even further out, the future is expected to bring vertical gates and other novel transistor structures. It is not yet clear how doping of these structures will be achieved. One alternative, the use of very high tilt angles, would run the risk of shadowing by adjacent structures. High tilt angles require accurate angular control, though current processes face that challenge as well.

For several process generations, junction formation has been a relatively stable technology. Though implantation and annealing have evolved as transistors have scaled, neither process has faced the revolutionary changes sweeping the rest of the industry. Yet change is the only constant in semiconductor manufacturing. Just as the introduction of sub-wavelength optical lithography brought the maskmakers' vacation to an abrupt end, new materials and new transistor structures are likely to have serious repurcussions for junction formation.

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  1. A. Satta et. al., "Device characteristics of ultrashallow junctions formed by fRTP annealing," Mat. Res. Soc. Symp. Proc., vol. 810, paper C1.3 (2004).
  2. Akio Shima, et. al. "Ultrashallow junction formation by self-limiting LTP and its application to sub-65nm node MOSFETs," IEEE Trans. Electron Dev., vol 52 (6), p. 1165 (2005).
  3. William J. Taylor, et. al., "Materials challenges for CMOS junctions," Mat. Res. Soc. Symp. Proc., vol. 810, paper C1.1 (2004).

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